Freescale Semiconductor /MKL28T7_CORE1 /LPIT0 /MIER

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Interpret as MIER

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)TIE0 0 (0)TIE1 0 (0)TIE2 0 (0)TIE3

TIE0=0, TIE1=0, TIE3=0, TIE2=0

Description

Module Interrupt Enable Register

Fields

TIE0

Channel 0 Timer Interrupt Enable

0 (0): Interrupt generation is disabled

1 (1): Interrupt generation is enabled

TIE1

Channel 1 Timer Interrupt Enable

0 (0): Interrupt generation is disabled

1 (1): Interrupt generation is enabled

TIE2

Channel 2 Timer Interrupt Enable

0 (0): Interrupt generation is disabled

1 (1): Interrupt generation is enabled

TIE3

Channel 3 Timer Interrupt Enable

0 (0): Interrupt generation is disabled

1 (1): Interrupt generation is enabled

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